Projects
SUBLEQ - Part II
Runtime
Now that there's a small logical model of what a true SUBLEQ computer would look like, we begin to run into some limitations. Since there is no explicit "load into mem" instruction, we begin to run into trouble almost immediately, since every computation needs a few constants along the way. To sidestep this issue, we are loading a separate RAM image and a ROM image into our computer model. Tedious - for now.
Since there's no official friendly compiler for the SUBLEQ computer yet, we will have to hand-write the raw machine code for the ROM, and fill in the RAM by hand. To test this machine, a fairly complex process is not necessary, we will be doing a simple addition 02h + 0Fh. This should return a result of +17d.
Note: As I found out the hard way, the Xilinx set of simulation tools is kinda weak when it comes to loading in files into memory arrays. All memory entries must be initialized at the same time, or fuse will just ignore it. No comments can be included in the file either (!). With these caveats in mind, let's write some SUBLEQ.
SUBLEQ - Part I
This project has been featured on HackADay on 7/27/2011.
2022: The content is presented as originally written with slight annotations for readability.
Introduction
An OISC (one instruction set computer) is an extremely simplified computer architecture. Instead of a fully-featured instruction set (also known as a complex instruction set), a OISC has only one operation; it is the RISC approach to computing taken to the extreme.
A SUBLEQ computer based on the OISC model has only one instruction, eliminating the need for an opcode field in the instruction. The model specified below has a datapath width of 8 bits, but the instruction word is 24 bits wide, and is formatted in terms of memory locations it addresses.
